Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with buried gates and buried bit lines, and a method for fabricating the semiconductor device.
Recently, semiconductor device fabrication processes are being developed to have an increased degree of integration. Among diverse methods for securing reliability and integration degree of a semiconductor device is a method of using buried gates. The parasitic capacitance between a gate and a bit line can be remarkably reduced by burying the gate in the inside of an active region. The gate buried in the inside of an active region is referred to as a buried gate. With the buried gate, the sensing margin of a memory device can be considerably improved.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device with buried gates.
Referring to FIG. 1, the semiconductor device includes a semiconductor substrate 11 with an active region 13 defined by an isolation layer 12, trenches 14 which are formed by simultaneously etching the active region 13 and the isolation layer 12, a buried gate 16 filling a portion of each trench 14, and a gap-filling layer 17 filling the other portion of the trench 14 over the buried gate 16. The semiconductor device also includes a gate insulation layer 15 formed between the buried gate 16 and the trench 14. In the active region 13, a bit line 18 is coupled with a storage node contact 19. The bit line 18 is coupled with the active region 13 through a bit line contact hole 18A. The bit line contact hole 18A is formed in a first inter-layer dielectric layer 20, and the storage node contact 19 is coupled with the active region 13 through a second inter-layer dielectric layer 21 and the first inter-layer dielectric layer 20
According to the conventional technology shown in FIG. 1, only the buried gate 16 is formed in the inside of the active region 13, and the bit line 18 is coupled with the active region 13 through the bit line contact hole 18A.
The conventional technology described above, however, has the following drawbacks.
First, when the bit line contact hole 18A is formed for high integration, the size of the contact hole should be formed small. In this case, when the contact hole is formed too small, the contact hole may not be opened, which is called a contact-hole-not-open phenomenon. In this case, it may be impossible to perform a mask process.
Second, when the bit line 18 is formed, a process of forming a nitride spacer 18B, which surrounds the bit line 18, needs to be performed to prevent a short from occurring between the storage node contact 19 and the bit line 18. With the nitride spacer forming process performed additionally, the cross-sectional area of a bit line may be reduced so as to increase resistance.
Third, since the bit line 18 is positioned in the upper portion of the active region 13, the connection portion with the active region 13 may become weak when a storage node contact hole for the storage node contact 19.
Fourth, the over-lay margins of the bit line 18 and the bit line contact hole 18A are so poor that the bit line 18 and the bit line contact hole 18A may be bridged with an adjacent storage node contact and thus a self-alignment contact failure of the storage node contact is highly likely to occur.